Added some missing Thumb instructions to the traceback follower, so now it is able to traceback through switch() statements
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etagle
parent
328edea03a
commit
8934a2c49b
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@ -25,10 +25,10 @@
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* \param value The value to sign extend.
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* \return The signed-11 bit value stored in a 16bit data type.
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*/
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static int16_t signExtend11(uint16_t value) {
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static int32_t signExtend11(uint16_t value) {
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if(value & 0x400) {
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value |= 0xf800;
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value |= 0xfffff800;
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}
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return value;
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@ -243,6 +243,40 @@ UnwResult UnwStartThumb(UnwState * const state) {
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UnwPrintd3(" r%d = 0x%08x\n", r, state->regData[r].v);
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}
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/*
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* TBB / TBH
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*/
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else if ((instr & 0xfff0) == 0xe8d0 && (instr2 & 0xffe0) == 0xf000) {
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/* We are only interested in
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* the forms
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* TBB [PC, ...]
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* TBH [PC, ..., LSL #1]
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* as those are used by the C compiler to implement
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* the switch clauses
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*/
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uint8_t rn = instr & 0xf;
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uint8_t rm = instr2 & 0xf;
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bool H = (instr2 & 0x10) ? true : false;
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UnwPrintd5("TB%c [r%d,r%d%s]\n", H ? 'H' : 'B', rn, rm, H ? ",LSL #1" : "");
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// We are only interested if the RN is the PC. Let´s choose the 1st destination
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if (rn == 15) {
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if (H) {
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uint16_t rv;
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if(!state->cb->readH((state->regData[15].v & (~1)) + 2, &rv)) {
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return UNWIND_DREAD_H_FAIL;
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}
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state->regData[15].v += rv * 2;
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} else {
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uint8_t rv;
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if(!state->cb->readB((state->regData[15].v & (~1)) + 2, &rv)) {
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return UNWIND_DREAD_B_FAIL;
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}
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state->regData[15].v += rv * 2;
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}
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}
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}
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/*
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* Unconditional branch
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*/
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@ -374,6 +408,118 @@ UnwResult UnwStartThumb(UnwState * const state) {
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UnwPrintd2(" New PC=%x", state->regData[15].v + 2);
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}
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}
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/*
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* PC-relative load
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* LDR Rd,[PC, #+/-imm]
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*/
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else if((instr & 0xff7f) == 0xf85f) {
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uint8_t rt = (instr2 & 0xf000) >> 12;
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uint8_t imm12 = (instr2 & 0x0fff);
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bool A = (instr & 0x80) ? true : false;
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uint32_t address;
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/* Compute load address, adding a word to account for prefetch */
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address = (state->regData[15].v & (~0x3)) + 4;
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if (A) address += imm12;
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else address -= imm12;
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UnwPrintd4("LDR r%d,[PC #%c0x%08x]", rt, A?'+':'-', address);
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if(!UnwMemReadRegister(state, address, &state->regData[rt])) {
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return UNWIND_DREAD_W_FAIL;
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}
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}
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/*
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* LDR immediate.
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* We are only interested when destination is PC.
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* LDR Rt,[Rn , #n]
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*/
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else if ((instr & 0xfff0) == 0xf8d0) {
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uint8_t rn = (instr & 0xf);
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uint8_t rt = (instr2 & 0xf000) >> 12;
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uint16_t imm12 = (instr2 & 0xfff);
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/* If destination is PC and we don't know the source value, then fail */
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if (!M_IsOriginValid(state->regData[rn].o)) {
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state->regData[rt].o = state->regData[rn].o;
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} else {
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uint32_t address = state->regData[rn].v + imm12;
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if(!UnwMemReadRegister(state, address, &state->regData[rt])) {
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return UNWIND_DREAD_W_FAIL;
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}
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}
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}
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/*
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* LDR immediate
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* We are only interested when destination is PC.
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* LDR Rt,[Rn , #-n]
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* LDR Rt,[Rn], #+/-n]
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* LDR Rt,[Rn, #+/-n]!
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*/
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else if ((instr & 0xfff0) == 0xf850 && (instr2 & 0x0800) == 0x0800) {
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uint8_t rn = (instr & 0xf);
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uint8_t rt = (instr2 & 0xf000) >> 12;
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uint16_t imm8 = (instr2 & 0xff);
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bool P = (instr2 & 0x400) ? true : false;
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bool U = (instr2 & 0x200) ? true : false;
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bool W = (instr2 & 0x100) ? true : false;
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if (!M_IsOriginValid(state->regData[rn].o)) {
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state->regData[rt].o = state->regData[rn].o;
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} else {
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uint32_t offaddress = state->regData[rn].v + imm8;
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if (U) offaddress += imm8;
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else offaddress -= imm8;
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uint32_t address;
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if (P) {
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address = offaddress;
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} else {
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address = state->regData[rn].v;
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}
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if(!UnwMemReadRegister(state, address, &state->regData[rt])) {
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return UNWIND_DREAD_W_FAIL;
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}
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if (W) {
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state->regData[rn].v = offaddress;
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}
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}
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}
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/*
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* LDR (register).
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* We are interested in the form
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* ldr Rt, [Rn, Rm, lsl #x]
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* Where Rt is PC, Rn value is known, Rm is not known or unknown
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*/
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else if ((instr & 0xfff0) == 0xf850 && (instr2 & 0x0fc0) == 0x0000) {
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uint8_t rn = (instr & 0xf);
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uint8_t rt = (instr2 & 0xf000) >> 12;
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uint8_t rm = (instr2 & 0xf);
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uint8_t imm2 = (instr2 & 0x30) >> 4;
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if (!M_IsOriginValid(state->regData[rn].o) ||
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!M_IsOriginValid(state->regData[rm].o)) {
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/* If Rt is PC, and Rn is known, then do an exception and assume
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Rm equals 0 => This takes the first case in a switch() */
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if (rt == 15 && M_IsOriginValid(state->regData[rn].o)) {
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uint32_t address = state->regData[rn].v;
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if(!UnwMemReadRegister(state, address, &state->regData[rt])) {
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return UNWIND_DREAD_W_FAIL;
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}
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} else {
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/* Propagate unknown value */
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state->regData[rt].o = state->regData[rn].o;
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}
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} else {
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uint32_t address = state->regData[rn].v + (state->regData[rm].v << imm2);
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if(!UnwMemReadRegister(state, address, &state->regData[rt])) {
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return UNWIND_DREAD_W_FAIL;
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}
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}
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}
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else {
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UnwPrintd1("???? (32)");
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@ -452,8 +598,8 @@ UnwResult UnwStartThumb(UnwState * const state) {
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}
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/* Propagate the origin */
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if(M_IsOriginValid(state->regData[rs].v) &&
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M_IsOriginValid(state->regData[rn].v)) {
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if(M_IsOriginValid(state->regData[rs].o) &&
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M_IsOriginValid(state->regData[rn].o)) {
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state->regData[rd].o = state->regData[rs].o;
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state->regData[rd].o |= REG_VAL_ARITHMETIC;
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}
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@ -715,8 +861,8 @@ UnwResult UnwStartThumb(UnwState * const state) {
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case 3: /* BX */
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UnwPrintd4("BX r%d\t; r%d %s\n", rhs, rhs, M_Origin2Str(state->regData[rhs].o));
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/* Only follow BX if the data was from the stack */
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if(state->regData[rhs].o == REG_VAL_FROM_STACK) {
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/* Only follow BX if the data was from the stack or BX LR */
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if(rhs == 14 || state->regData[rhs].o == REG_VAL_FROM_STACK) {
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UnwPrintd2(" Return PC=0x%x\n", state->regData[rhs].v & (~0x1));
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/* Report the return address, including mode bit */
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@ -724,10 +870,6 @@ UnwResult UnwStartThumb(UnwState * const state) {
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return UNWIND_TRUNCATED;
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}
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/* Store return address in LR register */
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state->regData[14].v = state->regData[15].v + 2;
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state->regData[14].o = REG_VAL_FROM_CONST;
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/* Update the PC */
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state->regData[15].v = state->regData[rhs].v;
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@ -927,7 +1069,7 @@ UnwResult UnwStartThumb(UnwState * const state) {
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*/
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else if((instr & 0xf800) == 0xe000) {
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uint32_t v;
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int16_t branchValue = signExtend11(instr & 0x07ff);
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int32_t branchValue = signExtend11(instr & 0x07ff);
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/* Branch distance is twice that specified in the instruction. */
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branchValue *= 2;
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